1. Field of the Invention
This invention relates to integrated circuits, and particularly to interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties.
2. Description of Background
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been implanted within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is described generally as “metallization”. As the complexity of integrated circuits has increased, the complexity of the metallization compositions has also increased.
Aluminum and aluminum alloys were once the material of choice for forming interconnects. However, due to the current focus on increasing circuit density and speed, the use of copper as the interconnect material has grown significantly since copper exhibits lower resistivity and lower susceptibility to electromigration failure as compared to aluminum. Despite these advantages, one drawback of using copper is that it readily diffuses into the surrounding dielectric material during subsequent processing steps. To inhibit the diffusion of copper, copper interconnects are often capped with a protective barrier layer referred to as a “capping” layer or a “passivation” layer, such as silicon nitride.
Silicon carbide deposited using chemical vapor deposition (CVD) from a trimethylsilane source, which is commercially available from Applied Materials under the tradename of BLOK®, is currently used as a capping layer over copper interconnects formed by the damascene process. The compound with less nitrogen (N) (less than about 5 mol %), i.e., SiaCbNcHd, is referred to as “BLOK”, and the compound with more N (about 10 mol % to about 25 mol %), i.e., SiwCxNyHz, is referred to as “NBLOK”. BLOK has a lower dielectric constant of less than 4.0, whereas NBLOK has a dielectric constant of about 5.0. While BLOK is not a good oxygen barrier but is a good copper (Cu) barrier, NBLOK is both a good oxygen barrier and a good Cu barrier. In order to achieve low k capping while still providing a good oxygen barrier and a good Cu barrier layer, a bilayer has been designed with 5 to 10 nm of NBLOK as a bottom layer and 30 to 35 nm of BLOK as a top layer. These two capping layers have also been combined to form a bilayer cap comprising a layer of SiaCbNcHd over a thinner layer of SiwCxNyHz that adheres well to the copper surface. While this bilayer cap provides a significant reduction in the effective k value of the dielectric stack, it can undesirably exhibit electromigration failure. One of the reasons for this failure is that a seam forms in the CVD deposited SiwCxNyHz layer (NBLOK) in the corners above the sidewalls of the copper interconnect. Thus, oxygen can migrate through the upper SiaCbNcHd (BLOK) layer and through the seams of the thin SiwCxNyHz (NBLOK) layer. As a result, the upper surface of the copper interconnect could become oxidized, thereby reducing adhesive forces between the Cu interconnect and the SiwCxNyHz (NBLOK) layer and adversely affecting the electromigration properties of the bilayer cap.